W25Q64BV Datasheet, PDF (17/61 Pages) Winbond – 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q64BV
11.2 INSTRUCTIONS
The instruction set of the W25Q64BV consists of twenty seven basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI
input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 4
through 30. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be terminated. This feature further protects the device from
inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status
Register is being written, all instructions except for Read Status Register will be ignored until the program
or erase cycle has completed.
11.2.1 Manufacturer and Device Identification
MANUFACTURER ID
(M7-M0)
Winbond Serial Flash
EFh
Device ID
Instruction
W25Q64BV
(ID7-ID0)
ABh, 90h
16h
(ID15-ID0)
9Fh
4017h
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Publication Release Date: July 08, 2010
Revision E