W9864G2IB Datasheet, PDF (19/42 Pages) Winbond – 512K × 4 BANKS × 32BITS SDRAM

W9864G2IB
10.3 Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
DQM
DQ0~31
tCMH
tDS
tDH
Valid
Data-in
tCMS
tCMH
(Clock Mask)
CLK
tCKH
tCKS
tCKH
CKE
DQ0~31
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tCMS
tDS
tDH
Valid
Data-in
tCKS
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
Control Timing of Output Data
(Output Enable)
CLK
DQM
DQ0~31
(Clock Mask)
CLK
tCMH
tCMS
tCMH
tAC
tOH
tAC
tOH
Valid
Data-Out
CKE
DQ0~31
tCKH
tCKS
tCKH
tAC
tOH
tAC
tOH
Valid
Data-Out
tCMS
tHZ
tOH
Valid
Data-Out
tAC
tLZ
OPEN
tCKS
Valid
Data-Out
tAC
tOH
tAC
tOH
Valid
Data-Out
tAC
tOH
Valid
Data-Out
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Publication Release Date: Sep. 17, 2009
Revision A01