W9864G2IB Datasheet, PDF (15/42 Pages) Winbond – 512K × 4 BANKS × 32BITS SDRAM

W9864G2IB
9.5 AC Characteristics and Operating Condition
(VDD = 3V±0.3V for-6, VDD = 2.7V-3.6V for -7 on TA = 0 to 70°C) (Notes: 5, 6)
PARAMETER
SYM.
Ref/Active to Ref/Active Command Period
t_RC
Active to Precharge Command Period
t_RAS
Active to Read/Write Command Delay Time
t_RCD
Read/Write(a) to Read/Write(b)Command Period t_CCD
Precharge to Active(b) Command Period
t_RP
Active(a) to Active(b) Command Period
t_RRD
Write Recovery Time
CL* = 2
t_WR
CL* = 3
-6
MIN. MAX.
60
42 100000
18
1
18
12
2
2
CLK Cycle Time
CL* = 2
t_CK
CL* = 3
7.5 1000
6
1000
CLK High Level Width
CLK Low Level Width
Access Time from CLK
t_CH
2
t_CL
2
CL* = 2
5.5
t_AC
CL* = 3
5
Output Data Hold Time
t_OH
2
CL* = 2
6
Output Data High Impedance Time
t_HZ
CL* = 3
5
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in-Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
t_LZ
0
t_SB
0
6
t_T
0.5
1
t_DS
1.5
t_DH
1.0
t_AS
1.5
t_AH
1.0
t_CKS
1.5
t_CKH
1.0
t_CMS
1.5
t_CMH
1.0
t_REF
64
Mode Register Set Cycle Time
Exit self refresh to ACTIVE command
t_RSC
2
t_XSR
72
*CL = CAS Latency
-7
MIN. MAX.
65
45 100000
20
1
20
14
2
2
10 1000
7
1000
2
2
6
5.5
2
6
5.5
0
0
7
0.5
1
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
64
2
75
UNIT
nS
t_CK
nS
t_CK
nS
nS
mS
t_CK
nS
NOTES
8
8
9
9
9
7
9
8
8
8
8
8
8
8
8
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Publication Release Date: Sep. 17, 2009
Revision A01