W83791D Datasheet, PDF (18/46 Pages) Winbond – W83791D Winbond H/W Monitoring IC

W83791D
(b) Serial bus read from a register
0
SCL
780
Preliminary
78
SCL (Continued)
SDA (Continued)
SDA
0
Start By
Master
0
10110
Frame 1
Serial Bus Address Byte
1 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Ack
Ack
by
Frame 2
by
791D
Internal Index Register Byte
791D
0
780
78
0
Repeat
start
by
Master
10110
Frame 3
Serial Bus Address Byte
1 R/W
Ack
by
791D
0
D7 D6 D5 D4 D3 D2 D1 D0
Frame 4
Data Byte
Ack
by ^{Stop by}
Master Master
Figure 2. Serial Bus Read from Internal Address Register
6.3 Speech Function
6.3.1 General Description
The W83791D is a derivative of Winbond's PowerSpeech^TM synthesizers. There are up to 5 hardware trigger
inputs, 17 Hardware Monitor event and 128 programmable software event trigger inputs. If more than two events
happen simultaneously, the priority set by the internal H/W is: SLOTOCC# > EVNTRAP1 > EVNTRAP2 >
EVNTRAP3 > EVNTRAP4 > EVNTRAP5 > TRIGREG(Index 09h) 128 events > VIN0 > VIN1> others (VIN2 –
VIN9,TEMP, FAN, case open). Software trigger is able to accommodate 128 event triggers, with timeout register
(index 08h) enabled in advance for allowance of time on detecting devices. That is, once the system’s power is on,
BIOS can fill trigger event and speech voice will not be sent till the system fails owing to timeout. In addition, to
prevent events from taking place simultaneously.
6.3.2 Event Trigger Queue
W83791D provides 8 byte FIFO queue to store event trigger, i.e, the first 8 event can be served by speech
and speech will clear FIFO queue after service. Coding of Speech program must assign correct CPU_MODE event
vector to issue correct speech voices correspondent to speech trigger events. For example, CPU_MODE event
vector =1 represents absence of CPU, then coding speech with CPU is absent voice. When W83791D detects no
CPU exists, it will send vector = 1 to speech synthesizer and play this voice data. Following is the block diagram of
the 8-Byte event trigger queue.
CLK 1 HZ
Enable Timeout
(Index 0Ah, b6)
8-bit Counter
Trigger
Timeout Register
(Index 08h)
Timeout
Comparator
8-Byte Event Trigger Queue
Figure 3. Event trigger Queue
11
TRIG_REG
Event
Trigger Data
(Index 09h, b6~0)
Publication Release Date: Aug, 2001
Revision 0.41