W956D6HB Datasheet, PDF (14/57 Pages) Winbond – Low-power features

W956D6HB
64Mb Async./Burst/Sync./A/D MUX
8.2.3 Mixed-Mode Operation
The device supports a combination of synchronous WRITE / READ and asynchronous WRITE / READ operations
when the BCR is configured for synchronous operation. The asynchronous WRITE operations require that the clock
(CLK) remain static (HIGH or LOW) during the entire sequence. The ADV# signal can be used to latch the target
address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between
mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode
operation facilitates a seamless interface to legacy burst mode Flash memory controllers.
8.2.4 WAIT Operation
The WAIT output on a ADMUX PSRAM device is typically connected to a shared, system level WAIT signal. The
shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous
bus.
8.2.4.1 Wired-OR WAIT Configuration
READY
Processor
CellularRAM
WAIT
WAIT
Other
Device
WAIT
Other
Device
External
Pull-Up/Pull-Down
Resistor
When a burst READ or WRITE operation has been initiated, WAIT goes active to indicate that the ADMUX PSRAM
device requires additional time before data can be transferred. For READ operations, WAIT will remain active until
valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will
be accepted into the ADMUX PSRAM device. When WAIT transitions to an inactive state, the data burst will progress
on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial
latency may cause data corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for burst READ
operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock
cycles until the refresh has completed. When the refresh operation has completed, the burst READ operation will
continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows
time for the new row to be accessed.
WAIT will be asserted after OE# goes LOW during asynchronous READ operations. WAIT will be High-Z during
asynchronous WRITE operations. WAIT should be ignored during all asynchronous operations.
By using fixed initial latency (BCR[14] = 1), this ADMUX PSRAM device can be used in burst mode without monitoring
the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst
and at the end of the row. If WAIT is not monitored, the controller must stop burst accesses at row boundaries on its
own.
- 14 -
Publication Release Date : May 29,2013
Revision : A01-003