W29EE512 Datasheet, PDF (11/22 Pages) Winbond – 64K X 8 CMOS FLASH MEMORY

W29EE512
Read Cycle Timing Parameters
(VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM. W29EE512-70 W29EE512-90 W29EE512-12 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
TRC 70
-
90
-
120
-
nS
Chip Enable Access Time
TCE
-
70
-
90
-
120 nS
Address Access Time
TAA
-
70
-
90
-
120 nS
Output Enable Access Time
TOE
-
35
-
40
-
50 nS
#CE High to High-Z Output
TCHZ
-
25
-
25
-
30 nS
#OE High to High-Z Output
TOHZ
-
25
-
25
-
30 nS
Output Hold from Address Change TOH 0
-
0
-
0
-
nS
Byte/Page-write Cycle Timing Parameters
PARAMETER
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
#WE and #CE Setup Time
#WE and #CE Hold Time
#OE High Setup Time
#OE High Hold Time
#CE Pulse Width
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
SYMBOL
TWC
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TWPH
TDS
TDH
TBLC
MIN.
-
0
50
0
0
0
0
90
90
100
35
0
-
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX.
10
-
-
-
-
-
-
-
-
-
-
-
200
Notes: All AC timing signals observe the following guidelines for determining setup and hold times:
(1) High level signal's reference level is VIH.
(2) Low level signal's reference level is VIL.
UNIT
mS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
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Publication Release Date: February 18, 2002
Revision A7