W83782D Datasheet, PDF (10/73 Pages) Winbond – MONITORING IC

Preliminary W83782D
5. PIN DESCRIPTION
I/O12t
I/O12ts
OUT12
AOUT
OD12
INt
INts
AIN
- TTL level bi-directional pin with 12 mA source-sink capability
- TTL level and schmitt trigger
- Output pin with 12 mA source-sink capability
- Output pin(Analog)
- Open-drain output pin with 12 mA sink capability
- TTL level input pin
- TTL level input pin and schmitt trigger
- Input pin(Analog)
PIN NAME
IOR#
IOW#
CLKIN
D7~D2
D1 /
PWMOUT4
D0 /
PWMOUT3
VID1
V_CC (+5V)
GNDD
MR
CASEOPEN#
VID4
PIN NO.
1
2
3
4-9
10
11
12
13
14
15
16
17
TYPE
IN_{t s}
IN_{t s}
IN _t
I/O_12t
I/O_12t
OUT₁₂
I/O_12t
OUT₁₂
IN_t
POWER
DGROUND
IN_{t s}
IN_t
IN _t
DESCRIPTION
An active low standard ISA bus I/O Read Control.
An active low standard ISA bus I/O Write Control.
System clock input. Can select 48MHz or 24MHz or 14.318MHz.
The default is 24MHz.
Bi-directional ISA bus Data lines. D0 corresponds to the low
order bit, with D7 the high order bit. These pins are activated if
pin ADRMSEL=0.
Bi-directional ISA bus Data lines. This pin is activated if pin
ADRMSEL=0.
/
Fan speed control PWM output. This pin is activated if pin
ADRMSEL=1.
Bi-directional ISA bus Data lines. This pin is activated if pin
ADRMSEL=0.
/
Fan speed control PWM output. This pin is activated if pin
ADRMSEL=1.
Voltage Supply readouts from P6. This value is read in the
VID/Fan Divisor Register.
+5V V_CC power. Bypass with the parallel combination of 10µF
(electrolytic or tantalum) and 0.1µF (ceramic) bypass capacitors.
Internally connected to all digital circuitry.
Master reset input.
CASE OPEN detection . An active low input from an external
device when case is opened. This signal can be latched if pin
VBAT is connect to battery, even W83782D is power off.
Voltage Supply readouts from P6. This value is read in the bit
<0> of Device ID Register.
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