WCMC8016V9X Datasheet, PDF (8/12 Pages) Weida Semiconductor, Inc. – 8Mb (512K x 16) Pseudo Static RAM

ADVANCE INFORMATION
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled) ^{[13, 14,16, 17, 18]}
ADDRESS
CE
t
WC
t_SCE
CE2
WE
t_{A W}
t_SA
t_PWE
BHE/BLE
t_BW
WCMC8016V9X
t_{H A}
OE
DATAI/O DON’T CARE
Write Cycle 2 (CE or CE₂ Controlled)^{[13, 14,16, 17, 18]}
ADDRESS
CE
t_SD
VALID DATA
t_WC
t_SCE
CE2
WE
t_SA
t_{A W}
t_PWE
BHE /BLE
t
BW
t_HD
t_{H A}
OE
DATA I/O
DON’T CARE
t_SD
t_HD
VALID DATA
t_{H Z O E}
Notes:
16. Data I/O is high impedance if OE = V_IH .
17. If Chip Enable goes INACTIVE and CE₂ goes LOW simultaneously with WE = V _IH, the output remains in a high-impedance state.
18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
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