WCMC8016V9X Datasheet, PDF (6/12 Pages) Weida Semiconductor, Inc. – 8Mb (512K x 16) Pseudo Static RAM

ADVANCE INFORMATION
WCMC8016V9X
Switching Characteristics Over the Operating Range^[11]
70 ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_DBE
t_LZBE
t_HZBE
t_SK
WRITE CYCLE^[13]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW and CE₂ HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z^{[12, 14]}
OE HIGH to High Z^{[12, 14]}
CE LOW and CE₂ HIGH to Low Z^{[12, 14]}
CE HIGH and CE₂ LOW to High Z^{[12, 14]}
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z^{[12, 14]}
BLE / BHE HIGH to HIGH Z^{[12, 14]}
Address Skew
70
ns
70
ns
10
ns
70
ns
35
ns
5
ns
25
ns
5
ns
25
ns
70
ns
5
ns
25
ns
10
ns
t_WC
Write Cycle Time
70
ns
t_SCE
CE LOW and CE₂ HIGH to Write End
60
ns
t_AW
Address Set-Up to Write End
60
ns
t_HA
Address Hold from Write End
0
ns
t_SA
Address Set-Up to Write Start
0
ns
t_PWE
WE Pulse Width
45
ns
t_BW
BLE / BHE LOW to Write End
60
ns
t_SD
Data Set-Up to Write End
45
ns
t_HD
t_HZWE
t_LZWE
Data Hold from Write End
WE LOW to High-Z^{[12, 14]}
WE HIGH to Low-Z^{[12, 14]}
0
ns
25
ns
5
ns
Notes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference leve ls of V _CC(typ)/2, input pulse
levels of 0 to V_{CC (typ.)} , and output loading of the specified I _OL/I_OH as shown in the “AC Test Loads and Waveforms” section..
12. t_HZOE, t_HZCE, t_HZBE, and t_HZWE transitions are measured when the outputs enter a high impedence state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = V_IL, BHE and/or BLE = V_IL, and CE₂ = V_IH . All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be refere nced to the edge of the
signal that terminates the write.
14. High-Z and Low-Z parameters are characterized and are not 100% tested.
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