W3E32M64S-XSBX Datasheet, PDF (17/17 Pages) White Electronic Designs Corporation – 32Mx64 DDR SDRAM

White Electronic Designs
W3E32M64S-XSBX
Document Title
32M x 64 DDR SDRAM Multi-Chip Package
Revision History
Rev #
Rev 0
Rev 1
History
Release Date Status
Initial Release
January 2004
Advanced
Changes (Pg. 1, 6, 10, 11, 12, 15, 16, 17)
1.1 Change status to Preliminary
1.2 Change maximum storage temperature to 125°C
1.3 Add 333Mbs/166MHz speed grade
1.4 Change typical weight to 1.5g
1.5 Add thermal resistance values
1.6 PCN04019 — Change maximum package body thickness
to 2.56mm
June 2005
Preliminary
Rev. 2
Rev 3
Rev 4
Rev 5
Changes (Pg. 1 - 17)
2.1 Change status to Final
2.2 Change 333Mbs CAS latency to 133/166 for Military
Temperature and 166/166 for Industrial Temerature.
2.3 ICC1 Burst Length change from 2 to 4
2.4 ICCS; TREFC = TRFC (Min) correction
2.5 Refresh to refresh command interval at Military
temperature tREFC = 35µs, tREFI = 3.9µs
2.6 Added AC Input Operating Conditions Table
2.7 Note number updates page 11, 12, 15
2.8 Data rate corrected form MHz to Mbs
2.9 Note 48 removed (Duplicate)
Changes (Pg. 3)
3.1 Correction to pin out
Changes (Pg. 1, 11, 15)
4.1 Correction of ViL Min
4.2 Added note on solder ball metallurgy
Changes (Pg. 1, 10, 17)
5.1 Update thermal resistance values to typical
September 2005 Final
June 2006
June 2006
July 2006
Final
Final
Final
July 2006
Rev. 5
17
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