W3E32M64S-XSBX Datasheet, PDF (12/17 Pages) White Electronic Designs Corporation – 32Mx64 DDR SDRAM

White Electronic Designs
W3E32M64S-XSBX
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 1-5, 14-17, 33)
Parameter
Access window of DQs from CLK/CLK#
CLK high-level width (30)
CLK low-level width (30)
CL = 3 (45, 51, 53)
Clock cycle time
CL = 2.5 (45, 51)
CL = 2 (45, 51)
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge from CLK rising - hold time
Half clock period (34)
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 42)
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command (46)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (49)
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble (43)
DQS read postamble (43)
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20, 21)
DQS write postamble (19)
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
REFRESH to REFRESH command interval (23) (commercial and
Industrial)
REFRESH to REFRESH command interval (Military temperature)
Average periodic refresh interval (23) (commercial and Industrial)
Average periodic refresh interval (Military temperature)
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Symbol
tAC
tCH
tCL
tCK (3)
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHF
tISF
tIHS
tISS
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
NA
tREFC
333 Mbs CL 3 (53)
266 Mbs CL2.5
Min Max
-0.70 +0.70
0.45 0.55
0.45 0.55
6
13
7.5
13
10
13
0.45
0.45
1.75
-0.6 +0.6
0.35
0.35
0.45
0.75 1.25
0.2
0.2
tCH,tCL
+0.70
-0.70
0.75
0.75
0.8
0.8
12
tHP-tQHS
0.55
42 70,000
15
60
72
15
15
0.9
1.1
0.4
0.6
12
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
70.3
266 Mbs CL 2.5
200 Mbs CL2
Min Max
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5
13
10
13
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.5
0.75 1.25
0.2
0.2
tCH,tCL
+0.75
-0.75
0.90
0.90
1
1
15
tHP-tQHS
0.75
40 120,000
20
65
75
20
20
0.9
1.1
0.4
0.6
15
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
70.3
250 Mbs CL2.5
200 Mbs CL2
Min Max
-0.8 +0.8
0.45 0.55
0.45 0.55
8
13
10
13
0.6
0.6
2
-0.8 +0.8
0.35
0.35
0.6
0.75 1.25
0.2
0.2
tCH,tCL
+0.8
-0.8
1.1
1.1
1.1
1.1
16
tHP-tQHS
1
40 120,000
20
70
80
20
20
0.9
1.1
0.4
0.6
15
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
70.3
200 Mbs CL2.5
150 Mbs CL2
Min Max
-0.8 +0.8
0.45 0.55
0.45 0.55
10
13
13
15
0.6
0.6
2
-0.8 +0.8
0.35
0.35
0.6
0.75 1.25
0.2
0.2
tCH,tCL
+0.8
-0.8
1.1
1.1
1.1
1.1
16
tHP-tQHS
1
40 120,000
20
70
80
20
20
0.9
1.1
0.4
0.6
15
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
70.3
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
tREFC
35
35
35
35
µs
tREFI
7.8
7.8
7.8
7.8
µs
tREFI
3.9
3.9
3.9
3.9
µs
tVTD
0
0
0
0
ns
tXSNR
75
75
80
80
ns
tXSRD
200
200
200
200
tCK
July 2006
Rev. 5
12
White Electronic Designs Corporation • [phone] • www.wedc.com