W3E32M64S-XSBX Datasheet, PDF (15/17 Pages) White Electronic Designs Corporation – 32Mx64 DDR SDRAM

White Electronic Designs
W3E32M64S-XSBX
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
50. ICC2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic
level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control
inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is
“worst case.”
51. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles before any READ command.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.
53. For 333Mbs operation of commercial and Industrial temperature CL = 2.5, at
Military temperature CL = 3.
PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA)
208 x Ø 0.6 (0.024) NOM
Bottom View
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1.0 (0.039)NOM
0.5 (0.020) NOM
10.0 (0.394) NOM
13.10 (0.516) MAX
2.56 (0.101) MAX
Note: This package utilizes solder balls which contain lead: Sn63Pb37
If you require lead free solder ball packages, please contact WEDC for information.
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
July 2006
Rev. 5
15
White Electronic Designs Corporation • [phone] • www.wedc.com