VSC6424 Datasheet, PDF (4/18 Pages) Vitesse Semiconductor Corporation – 500 Mb/s Video Shift Register IC

VITESSE
SEMICONDUCTOR CORPORATION
500 Mb/s Video
Shift Register IC
Preliminary Datasheet
VSC6424
Table 3: DEMUX Mode DIN to SB Cross Reference
S<2:0>
000
001
010
011
100
101
110
111
Modulus
10 1:4
8 1:5
5 1:8
4 1:10
2 1:16
2 1:20
1 1:32
1 1:40
DIN9
36-39
35-39
32-29
30-39
20-39
0-39
DIN8
32-35
30-34
DIN7
28-31
25-29
24-31
20-29
16-32
0-31
DIN6
24-27
DIN5
20-23
20-24
16-23
DIN4
16-19
14-19
10-19
0-19
DIN3
12-15
10-14
8-15
0-15
DIN2
8-11
DIN1
4-7
5-9
0-7
0-9
DIN0
0-3
0-4
Initialization
The VSC6424 requires that the SYNC/SLDN input be low for at least one clock cycle after power on, then
be set high for at least on clock period to initialize the device. This is an edge sensitive function. In internal tim-
ing mode this serves to start the internal clock dividers and set the shift register and low speed output clocks in
motion. Additional edges while in internal timing mode serves to synchronize the output clocks as described
below. Once this has been done the device takes (2n) cycles to stabilize. During this time the slow bus (SB)
should be set to zero. The first data is then latched from the slow bus (SB) at the end of the (2n) cycles. The
device is now set to run and will latch data from the slow bus (SB) every (n) cycles. See Table 5 to determine (n)
for a selected modulus.
In MUX mode with internal timing the VSC6424 chip can also be initialized by providing a slow speed
clock to the SYNC input. This slow speed clock must be synchronized with high speed clock and based on the
modulus that the MUX is set to. For example if the VSC6424 is set to 4:1 mode and the high speed clock is set
to 500MHz then the SYNC input must be 125MHz. The initialization at power on will still take (2n) cycles of
the high speed clock. This allows the system to dictate when the slow speed data is latched and where the shift-
ing begins.
In external timing mode the SLDN/SYNC signal serves to set the shift register in motion once the data has
been latched from the slow speed bus.
Page 4
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52236-0, Rev 3.0
7/13/99