VSC6424 Datasheet, PDF (16/18 Pages) Vitesse Semiconductor Corporation – 500 Mb/s Video Shift Register IC

VITESSE
SEMICONDUCTOR CORPORATION
500 Mb/s Video
Shift Register IC
Preliminary Datasheet
VSC6424
Table 10: Package Pin Identification
Signal
Pin
SEN
DIVC
63
OEN
INT
EXTN
A<0:4>
HBLANK
VBLANK
107
99
2, 1, 128, 127, 126
124
125
OPS
35
CLKOUT
78
CLKOUTN
79
I/O Level
Description
Shift enable. In external timing mode, SEN high stops
I
ECL
the shift register from shifting. In internal timing
mode, DIVC high divides the output clocks (CLKE,
CLKT)by 2.
I
ECL
Output Enable. OEN high forces the DOUT<0:7> low.
This signal is asynchronous.
I
TTL
Timing control. A high sets the chip for internal
timing, a low sets the chip for external timing.
I
TTL
Address pins. These pins get transferred to
DOUT<0:7> in Address Interface mode.
I TTL Horizontal blank function. Active low.
I TTL Vertical blank function. Active low.
Clock phase select. When this signal is low the low
I
TTL
speed outputs (DOUT<0:7>) are clocked with the
rising edge of the clock. Setting it high clocks them
with the falling edge of the clock.
O ECL High speed clock out (True)
O ECL High speed output clock (Complement)
Page 16
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52236-0, Rev 3.0
7/13/99