VSC6424 Datasheet, PDF (2/18 Pages) Vitesse Semiconductor Corporation – 500 Mb/s Video Shift Register IC

VITESSE
SEMICONDUCTOR CORPORATION
500 Mb/s Video
Shift Register IC
Preliminary Datasheet
VSC6424
Functional Description
The VSC6424 is a 40-bit user configurable shift register designed to provide general purpose serialization
or de-serialization for high speed designs. The VSC6424 provides both multiplexer (MUX) and demultiplexer
(DEMUX) operations in a single package. With the ability to generate timing signals internally or have them
provided externally the VSC6424 maintains the highest design flexibility.
The low speed signals (parallel data, configuration, external timing) use a TTL interface and the high-speed
signals (serial data, high-speed clock) use an ECL interface. Two power supplies are utilized, +3.3 Volts and -2
Volts, dissipating a maximum of 2.7 Watts. A -1.32V external reference voltage is necessary for the ECL inter-
face. The part is packaged in a 14mm x 20mm 128-pin plastic quad flat pack with an exposed heat spreader.
Shift Register Mode/Modulus Selection
The shift register can be setup to work as multiplexer or as a demultiplexer. The MODE pin controls the
direction of operation (MUX or DEMUX). The select pins S<0:2> put the shift register in one of 8 configura-
tions shown in Table 1
Table 1: Modulus of Operation
S2
S1
S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Multiplexer
MODE = 0
8 4:1
8 5:1
5 8:1
4 10:1
2 16:1
2 20:1
1 32:1
1 40:1
Demultiplexer
MODE = 1
10 1:4
8 1:5
5 1:8
4 1:10
2 1:16
2 1:20
1 1:32
1 1:40
Internal Timing
The VSC6424 can be set up to use either internal or external timing sources. The VSC6424 contains an
internal timing generator that provides load and output rates depending on the modulus selected for the shift
register. The timing generator takes an external high speed differential clock (CLK). Internal timing mode must
be used for designs above 250MHz.
The internal timing generator also provides two low-speed clock outputs, CLKT(TTL) and CLKE(ECL).
The low speed clock is brought out so that other ICs can use this to latch the low speed data while in DMUX
mode. The slow speed clock output can be the same as the internal clock, or 1/2 the internal frequency by set-
ting DIVC high. These outputs can also be shifted in 45 degree increments, using the phase select pins
SP<0:2>, to allow compensation for trace delays on the board. Phase rotation is not available in divide by 5 or
divide by 10 modes.
The internal high speed clock is also brought out to a differential ECL output (CLKOUT). This output is
provided for clocking of the high speed data into the next IC.
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52236-0, Rev 3.0
7/13/99