VSC6424 Datasheet, PDF (15/18 Pages) Vitesse Semiconductor Corporation – 500 Mb/s Video Shift Register IC

VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC6424
500 Mb/s Video
Shift Register IC
Package Pin Descriptions
Table 10: Package Pin Identification
Signal
VCC
VTT
VTTL
VREF
DIN<0:9>
DOUT<0:7>
SB<0:39>
MODE
AEN
RETIME
CLK
CLKN
S<0:2>
CLKE
CLKT
SP<0:2>
SYNC
SLDN
LLDN
SIN
Pin
I/O Level
Description
7, 9, 18, 30, 32, 44, 45,58, 59,
71, 72, 73, 82, 85, 94, 96, 108,
109, 122, 123
3, 6, 13, 26, 33, 70, 77, 90, 97
5, 8, 21, 31, 34, 48, 55, 69, 95,
98, 112, 119
4
101, 102, 103, 104, 105, 68, 67,
66, 65, 64
I
86, 84, 83, 81, 80, 76, 75, 74 O
89, 91, 92, 93, 110, 111, 113,
114, 115, 116, 117, 118, 120,
121, 10, 11, 12, 14, 15, 16, 17,
19, 20, 22, 23, 24, 25, 27, 28,
B
29, 46, 47, 49, 50, 51, 52, 53,
54, 56, 57
62
I
100
I
60
I
61
I
39, 40, 41
I
87
O
88
O
36, 37, 38
I
106
I
43
I
42
I
0V Ground Connection.
-2V Supply Connection.
+3.3V Supply Connection
-1.32V external ECL Reference voltage.
ECL The 10 Demultiplexer High-Speed Inputs.
ECL The 8 Multiplexer High-Speed Outputs.
TTL
Slow Bidirectional Bus. Multiplexer Input,
Demultiplexer Output.
TTL Mux/DMux select signal. 1 for DMUX, 0 for MUX.
Address enable. In Mux mode, while AEN is low, the
TTL clock transfers A<0:4> to DOUT<0,2,4,6,7>. In
DMUX mode it provides retimer input.
ECL Differential Clock Input (True)
ECL Differential Clock Input (Complement)
TTL Shift Register Modulus Control
ECL
Low Speed Clock. Clock used for latching the low
speed bus in internal timing mode.
TTL Low Speed Clock. TTL version of above.
TTL Phase select for output clocks (CLKE, CLKT)
Shift register load control. Used to transfer data from
input latch to shift register in external timing mode.
TTL Data is transferred on the rising edge of CLK while
SLDN is low. In internal timing mode, SYNC is the
synchronization input.
TTL
Input latch control. In external timing mode, LLDN
low makes the low speed input latches transparent.
Serial data in. The shift register can be serially loaded
ECL using this pin. The data is latched on rising edge of
CLK. Connect to VTT if not used.
G52236-0, Rev 3.0
7/13/99
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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