VSC6424 Datasheet, PDF (12/18 Pages) Vitesse Semiconductor Corporation – 500 Mb/s Video Shift Register IC

500 Mb/s Video
Shift Register IC
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC6424
Table 6: Timing Tables
Parameter
t_cyci
t_cyce
t_dis
t_dih
t_sbcs
t_sbch
t_sbls
t_sblh
t_cco
t_cdn
t_cdi
t_ccdn
t_ccdi
t_oed
t_dds
t_as
t_ah
t_aes
t_aeh
t_bls
t_blh
t_slds
t_sldh
t_sys
t_syh
t_sis
t_sih
t_csb
t_c-ce
t_ce-ct
Description
Minimum cycle time in internal timing mode
Minimum cycle time in external timing mode
DIN setup time
DIN hold time
SB setup with respect to CLK
SB hold time with respect to CLK
SB setup with respect to LLD
SB hold with respect to LLD
CLK to CLKOUT delay
CLK rising to DOUT, with OPS low
CLK falling to DOUT, with OPS high
CLKOUT to DOUT skew, with OPS low
CLKOUT to DOUT skew, with OPS high
OEN to DOUT
DOUT<x> to DOUT<y> skew
A<0:4> setup time
A<0:4> hold time
AEN setup time
AEN hold time
H/VBLANK setup
H/VBLANK hold
SLDN setup
SLDN hold
SYNC setup
SYNC hold
SIN setup
SIN hold
CLK to SB delay
CLK to CLKE delay
CLKE to CLKT skew
Min
Typ
Max
Units
2.0
-
-
ns
4.0
-
-
ns
200
-
-
ps
900
-
-
ps
600
-
-
ps
800
-
-
ps
100
-
-
ps
1200
-
-
ps
1100
-
3500
ps
1200
-
3700
ps
1300
-
3900
ps
-140
-
1100
ps
-50
-
1200
ps
900
-
3000
ps
-
-
100
ps
1100
-
-
ps
200
-
-
ps
900
-
-
ps
600
-
-
ps
1000
-
-
ps
200
-
-
ps
1300
-
-
ps
100
-
-
ps
800
-
-
ps
300
-
-
ps
700
-
-
ps
300
-
-
ps
1700
-
5800
ps
1500
-
5200
ps
400
-
2500
ps
Page 12
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52236-0, Rev 3.0
7/13/99