SI8435DB Datasheet, PDF (7/8 Pages) Vaishali Semiconductor – Dual P-Channel 20-V (D-S) MOSFET

PACKAGE OUTLINE
MICRO FOOT: 4-BUMP (2 x 2, 0.8 mm PITCH)
4 x ∅ 0.30 ~ 0.31
Note 3
Solder Mask ∅ ~ 0.40
e
A₂
A
A₁
e
Recommended Land
b Diameter
E
8435
XXX
Mark on Backside of Die
Notes (Unless Otherwise Specified):
1. Laser mark on the silicon die back, coated with a thin metal.
2. Bumps are Sn/Ag/Cu.
3. Non-solder mask defined copper landing pad.
4. The flat side of wafers is oriented at the bottom.
Dim.
A
A₁
A₂
b
D
E
e
S
Min.
0.600
0.260
0.340
0.370
1.520
1.520
0.750
0.370
Notes:
a. Use millimeters as the primary measurement.
Millimeters^a
Max.
0.650
0.290
0.360
0.410
1.600
1.600
0.850
0.380
Si8435DB
Vishay Siliconix
Silicon
Bump Note 2
S
e
e
S
D
Min.
0.0236
0.0102
0.0134
0.0146
0.0598
0.0598
0.0295
0.0146
Inches
Max.
0.0256
0.0114
0.0142
0.0161
0.0630
0.0630
0.0335
0.0150
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?73559.
Document Number: 73559
S-82119-Rev. D, 08-Sep-08
www.vishay.com
7