SI4726CY Datasheet, PDF (4/9 Pages) Vishay Siliconix – N-Channel Synchronous MOSFETs with Break-Before-Make

Si4726CY
Vishay Siliconix
DETAILED BLOCK DIAGRAM
V_DD
Undervoltage
Lockout
Level Shift
IN
SYNC EN
V_DD
C_BOOT
V_DC
V_OUTH
V_S
Q₁
S₁
D₂
V_OUTL
Q₂
GND
+
- _VBBM
FIGURE 1.
PIN CONFIGURATION
D_{1 1}
D_{1 2}
GND ₃
IN ₄
SYNC EN ₅
S_{2 6}
S_{2 7}
S_{2 8}
SO-16
16 ^S1
15 ^S1
14 ^CBOOT
13 ^VDD
12 ^D2
11 ^D2
10 ^D2
9 ^D2
Top View
Order Number: Si4726CY
www.vishay.com
4
TRUTH TABLE
Sync EN
V_IN
Q₁
Q₂
H
H
ON
OFF
H
L
OFF
ON
L
H
ON
OFF
L
L
OFF
OFF
PIN DESCRIPTION
Pin Number Symbol
Description
1, 2
3
4
5
6, 7, 8
9, 10, 11, 12
13
14
15, 16
D₁
GND
IN
SYNC EN
S₂
D₂
V_DD
C_BOOT
S₁
Highside MOSFET Drain
Ground
Input Logic Signal
Synchronous Enable
Lowside MOSFET Source
Lowside MOSFET Drain
Logic Supply
Bootstrap Capacitor For Upper MOSFET
Highside MOSFET Source
Document Number: 71285
S-03075—Rev. C, 03-Feb-03