SI5855CDC Datasheet, PDF (2/9 Pages) Vishay Siliconix – P-Channel 20-V (D-S) MOSFET With Schottky Diode

Si5855CDC
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambient (MOSFET)^{b, c, f}
R_thJA
82
99
Maximum Junction-to-Foot (Drain) (MOSFET)
Maximum Junction-to-Ambient (Schottky)^{b, c, g}
R_thJF
35
R_thJA
54
45
°C/W
65
Maximum Junction-to-Foot (Drain) (Schottky)
R_thJF
30
40
Notes:
a. Based on T_C = 25 °C.
b. Surface Mounted on FR4 board.
c. t ≤ 5 s.
d. See Solder Profile (http://www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is
exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be
guaranteed and is not required to ensure adequate bottom side solder interconnection. Rework Conditions: manual soldering with a soldering
iron is not recommended for leadless components.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions for MOSFETS is 130 °C/W.
g. Maximum under Steady State conditions for Schottky is 115 °C/W.
SPECIFICATIONS T_J = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Static
Drain-Source Breakdown Voltage
V_DS
V_GS = 0 V, I_D = - 250 µA
V_DS Temperature Coefficient
V_GS(th) Temperature Coefficient
ΔV_DS/TJ
ΔV_GS(th)/TJ
I_D = - 250 µA
Gate-Source Threshold Voltage
V_GS(th)
V_DS = V_GS, I_D = - 250 µA
Gate-Body Leakage
I_GSS
V_DS = 0 V, V_GS = ± 8 V
Zero Gate Voltage Drain Current
I_DSS
V_DS = - 20 V, V_GS = 0 V
V_DS = - 20 V, V_GS = 0 V, T_J = 55 °C
On-State Drain Current^a
I_D(on)
V_DS ≤ - 5 V, V_GS = - 4.5 V
V_GS = - 4.5 V, I_D = - 2.5 A
Drain-Source On-State Resistance^a
R_DS(on)
V_GS = - 2.5 V, I_D = - 2.2 A
V_GS = - 1.8 V, I_D = - 2.0 A
Forward Transconductance^a
g_fs
V_DS = - 10 V, I_D = - 2.5 A
Dynamic^b
Input Capacitance
C_iss
Output Capacitance
C_oss
V_DS = - 10 V, V_GS = 0 V, f = 1 MHz
Reverse Transfer Capacitance
C_rss
Total Gate Charge
Q_g
V_DS = - 10 V, V_GS = - 5 V, I_D = - 2.5 A
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Q_gs
Q_gd
R_g
t_d(on)
t_r
t_d(off)
t_f
t_d(on)
t_r
t_d(off)
t_f
V_DS = - 10 V, V_GS = - 4.5 V, I_D = - 2.5 A
f = 1 MHz
V_DD = - 10 V, R_L = 5 Ω
I_D ≅ - 2 A, V_GEN = - 4.5 V, R_g = 1 Ω
V_DD = - 10 V, R_L = 5 Ω
I_D ≅ - 2 A, V_GEN = - 5 V, R_g = 1 Ω
Min. Typ. Max. Unit
- 20
- 0.45
- 10
- 19
2
0.120
0.150
0.185
18
-1
± 100
-1
- 10
0.144
0.180
0.222
V
mV/°C
V
ns
µA
A
Ω
S
276
60
pF
43
4.5
6.8
4.1
6.2
nC
0.6
1.0
1.1
5.5
11
Ω
11
17
34
51
22
33
8
16
ns
5
10
14
21
17
26
8
16
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Document Number: 68910
S-82299-Rev. A, 22-Sep-08