SI4559EY Datasheet, PDF (2/6 Pages) Vishay Siliconix – N-Channel 60-V (D-S), 175°C MOSFET

Si4559EY
Vishay Siliconix
SPECIFICATIONS (T_J = 25_C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Static
Gate Threshold Voltage
V_GS(th)
V_DS = V_GS, I_D = 250 mA
V_DS = V_GS, I_D = –250 mA
Gate-Body Leakage
I_GSS
V_DS = 0 V, V_GS = "20 V
Zero Gate Voltage Drain Current
On-State Drain Current^b
Drain-Source On-State Resistance^b
Forward Transconductance^b
Diode Forward Voltage^b
Dynamic^a
I_DSS
I_D(on)
r_DS(on)
g_fs
V_SD
V_DS = 60 V, V_GS = 0 V
V_DS = –60 V, V_GS = 0 V
V_DS = 60 V, V_GS = 0 V, T_J = 55_C
V_DS = –60 V, V_GS = 0 V, T_J = 55_C
V_DS w 5 V, V_GS = 10 V
V_DS v –5 V, V_GS = –10 V
V_GS = 10 V, I_D = 4.5 A
V_GS = –10 V, I_D = –3.1 A
V_GS = 4.5 V, I_D = 3.9 A
V_GS = –4.5 V, I_D = –2.8 A
V_DS = 15 V, I_D = 4.5 A
V_DS = –15 V, I_D = –3.1 A
I_S = 2.0 A, V_GS = 0 V
I_S = –2.0 A, V_GS = 0 V
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Q_g
N-Channel
V_DS = 30 V, V_GS = 10 V, I_D = 4.5 A
Q_gs
P-Channel
V_DS = –30 V, V_GS = –10 V
I_D = –3.1A
Q_gd
Turn-On Delay Time
t_d(on)
Rise Time
t_r
Turn-Off Delay Time
t_d(off)
Fall Time
t_f
Source-Drain Reverse Recovery Time
t_rr
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width v 300 ms, duty cycle v 2%.
N-Channel
V_DD = 30 V, R_L = 30 W
I_D ^ 1 A, V_GEN = 10 V, R_G = 6 W
P-Channel
V_DD = –30 V, R_L = 30 W
I_D ^ –1 A, V_GEN = –10 V, R_G = 6 W
I_F = 2 A, di/dt = 100 A/ms
I_F = –2 A, di/dt = 100 A/ms
Min Typ^a Max Unit
N-Ch
1
V
P-Ch
–1
N-Ch
P-Ch
"100
nA
"100
N-Ch
P-Ch
N-Ch
P-Ch
2
–2
mA
25
–25
N-Ch
20
A
P-Ch
–20
N-Ch
P-Ch
N-Ch
P-Ch
0.045 0.055
0.100 0.120
W
0.055 0.075
0.125 0.150
N-Ch
13
S
P-Ch
7.5
N-Ch
P-Ch
0.9
1.2
V
–0.8
–1.2
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
19
30
16
25
4
nC
4
3
1.6
13
20
8
15
11
20
10
20
36
60
ns
12
25
11
20
35
50
35
60
60
90
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2-2
Document Number: 70167
S-57253—Rev. D, 24-Feb-98