SI5411EDU Datasheet, PDF (1/9 Pages) Vishay Siliconix – P-Channel 12 V (D-S) MOSFET

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Si5411EDU
Vishay Siliconix
P-Channel 12 V (D-S) MOSFET
PRODUCT SUMMARY
V_DS (V)
- 12
R_DS(on) () (Max.)
0.0082 at V_GS = - 4.5 V
0.0094 at V_GS = - 3.7 V
0.0117 at V_GS = - 2.5 V
0.0206 at V_GS = - 1.8 V
I_D (A)
- 25^a
- 25^a
- 25^a
- 15
PowerPAK ChipFET Single
Q_g (Typ.)
43 nC
FEATURES
• TrenchFET^® Power MOSFET
• Thermally Enhanced PowerPAK^® ChipFET Package
- Small Footprint Area
- Low On-Resistance
• 100 % R_g and UIS Tested
• Typical ESD Protection: 5000 V (HBM)
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
1
2
D
3
D
D
4
8
D
7
D
6
S
5
D
G
S
1.9 ^mm
APPLICATIONS
S
• Portable Devices such as Smart Phones,
Tablet PCs and Mobile Computing
- Battery Switch
- Load Switch
- Power Management
G
Marking Code
Bottom View
Ordering Information:
Si5411EDU-T1-GE3 (Lead (Pb)-free and Halogen-free)
LB XXX
Lot Traceability
and Date Code
Part # Code
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (T_C = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
Gate-Source Voltage
V_DS
- 12
V
V_GS
±8
T_C = 25 °C
- 25^a
Continuous Drain Current (T_J = 150 °C)
T_C = 70 °C
T_A = 25 °C
I_D
- 25^a
- 16.5^{b, c}
Pulsed Drain Current (t = 100 μs)
T_A = 70 °C
- 13^{b, c}
A
I_DM
- 140
Continuous Source-Drain Diode Current
T_C = 25 °C
T_A = 25 °C
I_S
- 25^a
- 2.6^{b, c}
Single Avalanche Current
Single Avalanche Energy
L = 0.1 mH
I_AS
- 15
E_AS
11
mJ
T_C = 25 °C
31
Maximum Power Dissipation
T_C = 70 °C
T_A = 25 °C
P_D
20
3.1^{b, c}
W
T_A = 70 °C
2^{b, c}
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)^{d, e}
T_J, T_stg
- 50 to 150
°C
260
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambient^{b, f}
Maximum Junction-to-Case (Drain)
t5s
R_thJA
34
Steady State
R_thJC
3
40
°C/W
4
Notes
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 90 °C/W.
S13-1662-Rev. A, 29-Jul-13
1
Document Number: 62879
For technical questions, contact: [e-mail]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000