PI354X-00 Datasheet, PDF (26/39 Pages) –

Input Overvoltage Lockout
If V_IN exceeds the input Overvoltage Lockout (OVLO) threshold
(V_OVLO), while the controller is running, the PI354x-00 will
complete the current cycle and stop switching. The system will
soft start after the Fault Restart Delay once V_IN recovers. The
PI354x products permit input voltage positive transient excursions
beyond V_{IN_DC} maximum, up to V_IN-TRANS maximum. In this case,
the input voltage is allowed to be outside the V_{IN_DC} range for
up to 10ms, with no more than a 1% duty cycle. Note that any
excursion beyond the V_{IN_DC} maximum must still adhere to the
maximum slew rate V_{IN_SR}.
Output Overvoltage Protection
The PI354x-00 family is equipped with output Overvoltage
Protection (OVP) to prevent damage to input voltage
sensitive devices. If the output voltage exceeds 20% of its set
regulated value, the regulator will complete the current cycle
and stop switching. The system will resume operation once
the output voltage falls below the OVP threshold and after
Fault Restart Delay.
Overtemperature Protection
The PI354x features an over temperature protection (OTP), which
will not engage until after the product is operated above the
maximum rated temperature. The OTP circuit is only designed to
protect against catastrophic failure due to excessive temperatures
and should not be relied upon to ensure the device stays within
the recommended operating temperature range. Thermal
shutdown terminates switching and discharges the soft-start
capacitor. As the temperature falls the PI354x will restart,
and this will always occur before the product returns to rated
temperature range.
Pulse Skip Mode (PSM)
PI354x-00 features a PSM to achieve high efficiency at light loads.
The regulators are setup to skip pulses if EAO falls below a PSM
threshold. Depending on conditions and component values, this
may result in single pulses or several consecutive pulses followed
by skipped pulses. Skipping cycles significantly reduces gate drive
power and improves light load efficiency. The regulator will leave
PSM once the EAO rises above the Skip Mode threshold.
V_IN
C_IN
SYNCO #2
SYNCI #2
R1
EN #2
VIN
PGND _PI354X
VDR
SYNCO
SYNCI
PWRGD
EN
TESTx
SGND
(#1)
VS1
VOUT
VSN
VSP
VDIFF
LGH
EAIN
EAO
COMP
TRK
L1
EAO #2
C_OUT
V_OUT
TRK #2
V_IN
C_IN
L1
VIN
VS1
PGND _PI354X VOUT
VDR
VSN
C_OUT
VSP
To R1
SYNCO #1
(#2) ^SYNCO
SYNCI
VDIFF
LGH
PWRGD
EAIN
EN #1
EN
EAO
EAO #1
TESTx
COMP
SGND
TRK
TRK #1
Figure 50 — PI354x-00 parallel operations
PI354x-00
Variable Frequency Operation
Each PI354x-00 is preprogrammed to a base operating frequency,
with respect to the power stage inductor (see Table 2), to operate
at peak efficiency across line and load variations. At low line
and high load applications, the base frequency will decrease to
accommodate these extreme operating ranges. By stretching the
frequency, the ZVS operation is preserved throughout the total
input line voltage range therefore maintaining
optimum efficiency.
Application Description
Parallel Operation
PI354x-00 can be connected in parallel to increase the output
capability of a single output rail. When connecting modules in
parallel, each EAO, TRK, EAIN and EN pin should be connected
together. Current sharing will occur automatically in this manner
so long as each inductor is the same value. A common viewing
chain may be used to sense the output voltage. Refer to the
Electrical Characteristics table for maximum array size and
array rated output current. Current sharing may be considered
independent of synchronization and/or interleaving. Modules do
not have to be interleaved or synchronized to share current.
Synchronization
PI354x-00 units may be synchronized to an external clock by
driving the SYNCI pin. The synchronization frequency must not
be higher than the programmed maximum value F_SW. This is the
switching frequency during DCM of operation. The minimum
synchronization frequency is F_SW /2. In order to ensure proper
power delivery during synchronization, the user should refer
to the switching frequency vs. output current curves for the
load current, output voltage and input voltage operating point.
The synchronization frequency should not be lower than that
determined by the curve or reduced output power will result.
The power reduction is approximately the ratio between required
frequency and synchronizing frequency. If the required frequency
is 1MHz and the sync frequency is 600kHz, the user should
expect a 40% reduction in output capability.
Interleaving
Interleaving is primarily done to reduce output ripple and the
required number of output capacitors by introducing phase
current cancellation. The PI354x-00 has a fixed delay that is
proportional to to the maximum value of F_SW shown in the data
sheet. When connecting two units as shown in Figure 50, they
will operate at 180 degrees out of phase when the converters
switching frequency is equal to F_SW. If the converter enters CrCM
and the switching frequency is lower than F_SW, the phase delay
will no longer be 180 degrees and ripple cancellation will begin
to decay. Interleaving when the switching frequency is reduced
to lower than 80% of the programmed maximum value is
not recommended.
Cool-Power^® ZVS Switching Regulators
Page 26 of 39
Rev 1.6
03/2017
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