TC59LM913AMG-50 Datasheet, PDF (9/46 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

TC59LM913AMG-50
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
SYMBOL
PARAMETER
t_LZ
t_HZ
t_QSLZ
t_QSHZ
t_QPDH
t_PDEX
t_T
t_FPDL
t_REFI
t_PAUSE
I_RC
I_RCD
I_RAS
I_RBD
Data-out Low Impedance Time from CLK
Data-out High Impedance Time from CLK
DQS-out Low Impedance Time from CLK
DQS-out High Impedance Time from CLK
Last output to PD High Hold Time
Power Down Exit Time
Input Transition Time
PD Low Input Window for Self-Refresh Entry
Auto-Refresh Average Interval
Pause Time after Power-up
Random Read/Write Cycle Time
(applicable to same bank)
RDA/WRA to LAL Command Input Delay
(applicable to same bank)
LAL to RDA/WRA Command Input Delay
(applicable to same bank)
Random Bank Access Delay
(applicable to other bank)
I_RWD
I_WRD
I_RSC
I_PD
I_PDA
I_PDV
LAL following RDA to WRA Delay
(applicable to other bank)
B_L = 2
B_L = 4
LAL following WRA to RDA Delay
(applicable to other bank)
Mode Register Set Cycle Time
C_L = 3
PD Low to Inactive State of Input Buffer
PD High to Active State of Input Buffer
Power down mode valid from REF command
I_REFC
I_CKD
I_LOCK
Auto-Refresh Cycle Time
REF Command to Clock Input Disable at Self-Refresh Entry
DLL Lock-on Time (applicable to RDA command)
MIN
−0.65

−0.65
−0.65
0
0.9
0.1
−0.5 × t_CK
0.4
200
5
1
4
2
2
3
1
5


18
18
16
200
MAX

0.65

0.65


1
5
3.9


1






1
1




UNIT NOTES
3,6,8
3,7,8
3,6,8
3,7,8
ns
3
3
5
µs
cycle
Rev 1.1
2005-11-08 9/46