TC59LM913AMG-50 Datasheet, PDF (1/46 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

TC59LM913AMG-50
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
512Mbits Network FCRAM1 (SSTL_2 Interface)
− 4,194,304-WORDS × 8 BANKS × 16-BITS
Lead-Free
DESCRIPTION
Network FCRAM^TM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913AMG is Network
FCRAM^TM containing 536,870,912 memory cells. TC59LM913AMG is organized as 4,194,304-words × 8 banks × 16
bits. TC59LM913AMG feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM913AMG can operate fast core cycle compared with regular DDR SDRAM.
TC59LM913AMG is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAM^TM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
TC59LM913AMG-50
t_CK Clock Cycle Time (min)
CL = 4
5.0 ns
t_RC Random Read/Write Cycle Time (min)
25.0 ns
t_RAC Random Access Time (max)
22.0 ns
I_DD1S Operating Current (single bank) (max)
240 mA
l_DD2P Power Down Current (max)
80 mA
l_DD6 Self-Refresh Current (max)
20 mA
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
• Fast cycle and Short Latency
• Eight independent banks operation
When BA2 input assign to A14 input, TC59LM913AMG can function as 4bank device
(Keep backward compatibility to 256Mb)
• Bidirectional Data Strobe Signal
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 4
Burst Length = 2, 4
• Organization: TC59LM913AMG : 4,194,304 words × 8 banks × 16 bits
• Power Supply Voltage VDD: 2.5 V ± 0.15V
VDDQ: 2.5 V ± 0.15 V
• 2.5 V CMOS I/O comply with SSTL_2 (half strength driver)
• Package: 60Ball BGA, 1mm × 1mm Ball pitch (P−BGA64−1317−1.00AZ)
• Lead-Free
• Keep backward compatibility for TC59LM814CFT(256Mbits) except package design.
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
Rev 1.1
2005-11-08 1/46