TC59LM913AMG-50 Datasheet, PDF (23/46 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

SINGLE BANK WRITE TIMING (CL = 4)
TC59LM913AMG-50
CLK
CLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
I_RC = 5 cycles
I_RC = 5 cycles
I_RC = 5 cycles
Command WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
WRA
Address UA LA
UA LA
UA LA
UA
Bank Add.
#0
BL = 2
DQS
(input)
DQ
(input)
BL = 4
DQS
(input)
DQ
(input)
#0
#0
#0
WL = 3
D0 D1
WL = 3
D0 D1
WL = 3
D0 D1
WL = 3
D0 D1 D2 D3
WL = 3
D0 D1 D2 D3
WL = 3
D0 D1 D2 D3
Rev 1.1
2005-11-08 23/46