TC59LM913AMG-50 Datasheet, PDF (31/46 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

TC59LM913AMG-50
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9 10 n-2 n-1 n n+1 n+2
CLK
CLK
I_PDA
Command WRA LAL
DESL
RDA
DESL ^or
WRA
Address UA LA
PD
WL = 3
t_IS I_PD = 1 cycle
t_IH
2 clock cycles
l_RC(min) , t_REFI(max)
DQS
(input)
DQ
(input)
WL = 3
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within t_REFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
UA
t_PDEX
Rev 1.1
2005-11-08 31/46