TX4939XBG-400 Datasheet, PDF (86/740 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Pin Assignment
Toshiba RISC Processor
TX4939
3.4.3. Pin Multiplex for ATA100-0 (Channel 0)
At the Boot time, the ATA100-0 port will be configured as GPIO channel-0. This port will be activated by setting ATA0MODE
bit in Pin Configuration Register (Chapter 7)
Table 3-5 Pin Multiplex for ATA100-0 Channel
Default Signal Name
GPIO (Boot default) ATA100-0
Ball
3
A0_DASP*
A0_DCS1*
A0_DCS0*
A0_DA2
A0_DA0
A0_PDIAG*
A0_DA1
A0_DINTR
A0_DMACK*
A0_DIORDY
A0_DIOR*
A0_DIOW*
A0_DMAREQ
A0_DD15
A0_DD00
A0_DD14
A0_DD01
A0_DD13
A0_DD02
A0_DD12
A0_DD03
A0_DD11
A0_DD04
A0_DD10
A0_DD05
A0_DD09
A0_DD06
A0_DD08
A0_DD07
A0_DRST*
G0PIO00
G0PIO01
G0PIO02
G0PIO03
G0PIO04
G0PIO05
G0PIO06
G0PIO07
G0PIO08
G0PIO09
G0PIO10
G0PIO11
G0PIO12
G0PIO13
G0PIO14
G0PIO15
G0PIO16
G0PIO17
G0PIO18
G0PIO19
G0PIO20
G0PIO21
G0PIO22
G0PIO23
G0PIO24
G0PIO25
G0PIO26
G0PIO27
G0PIO28
G0PIO29
A0_DASP*
A0_DCS1*
A0_DCS0*
A0_DA2
A0_DA0
A0_PDIAG*
A0_DA1
A0_DINTR
A0_DMACK*
A0_DIORDY
A0_DIOR*
A0_DIOW*
A0_DMAREQ
A0_DD15
A0_DD00
A0_DD14
A0_DD01
A0_DD13
A0_DD02
A0_DD12
A0_DD03
A0_DD11
A0_DD04
A0_DD10
A0_DD05
A0_DD09
A0_DD06
A0_DD08
A0_DD07
A0_DRST*
AF3
AD4
AE4
AF4
AC5
AD5
AE5
AF5
AC6
AD6
AE6
AF6
AC7
AD7
AF7
AC8
AD8
AE8
AF8
AC9
AD9
AE9
AF9
AC10
AD10
AE10
AF10
AC11
AD11
AE11
Note : All GPIO port is Hiz mode at boot time.
Rev. 3.1 November 1, 2005
3-14