TX4939XBG-400 Datasheet, PDF (603/740 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Toshiba RISC Processor
SPI
TX4939
Bit(s) Mnemonic
1
SPHA
Table 20-5 SPI Control Register 0 (SPCR0)
Field Name
SPI Phase
Description
0: LSB first (transfer starting from the least significant bit)
1: MSB first (transfer starting from the most significant bit)
SPI Clock Phase (Default: 0)
Selects the clock phase.
0
SPOL
SPI Polarity
0: Samples at the first clock edge, then shifts at the second edge.
1: Shifts at the first clock edge, then samples at the second edge.
SPI Clock Polarity (Default: 0)
Selects the SPICLK polarity.
0: High Active (SPICLK is Low when idle)
1: Low Active (SPICLK is High when idle)
Note 1: You can only write to bits 4, 2, 1, or 0 when the SPI Module is in the Configuration Mode.
Note 2: The SPOL and SPHA bits select the SPICLK phase and the clock edge at which to sample data. For details,
see 20.3.4
20.4.3. SPI Control Register 1 (SPCR1)
0xF808
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name:
RESERVED
R/W:
Default:
Bit:
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name:
SER
RESERVED
SSZ
R/W:
Default:
R/W
0x00
Figure 20-6 SPI Control Register 1 (SPCR1)
R/W
00000
Bits
31 : 16
15 : 8
Mnemonic
⎯
SER
Table 20-6 SPI Control Register 1 (SPCR1)
Field Name
Reserved
SPI Data Rate
Description
⎯
SPI Data Rate (Default: 000000b)
This field sets the transfer bit rate. The transfer bit rate is calculated according to the
following equation.
f_BR = f_SPI/2 (n + 1)
f_{BR :} SPICLK Frequency
f_{SPI :} SPI Master Clock Frequency
n
: SER (Setting “0” is not permitted)
(See 20.3.3 for SER and clock frequency examples.)
7:5
⎯
Reserved
⎯
4:0
SSZ
SPI Transfer
SPI Transfer Size (Default: 00000b)
Size
Selects the transfer size.
0x08: 8 bits
20
0x10: 16 bits
Other values: Reserved (not settings are permitted)
Note 1: You can only write to this register when the SPI Module is in the Configuration Mode.
Rev. 3.1 November 1, 2005
20-11