TX4939XBG-400 Datasheet, PDF (115/740 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Address
Toshiba RISC Processor
TX4939
6.3.4. DDR Mapping Window #n (n=0, 1, 2, 3) DRWIN00 0x8208
DRWIN01 0x8210
DRWIN02 0x8218
DRWIN03 0x8220
DRWIN00, DRWIN01, DRWIN02, and DRWIN03 control DDR Mapping condition independently.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
DRWINLO [35:30]
DRWINLO [29:20]
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
: R/W
: Default
6
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
COPY of DRWINLO [35:30]
DRWINUP [29:20]
R/O R/O R/O R/O R/O R/O R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
DRWINOF [29:20]
: R/W
: Default
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
: R/W
: Default
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESERVED
CS [1:0]
R/W
: R/W
0
: Default
Figure 6-4 DDR Mapping Window Control
Table 6-3 DDR Mapping Window Control
Bit Mnemonic Field Name
Description
63:48 DRWINLO
47:42 DRWINUP
41:32 DRWINUP
31:26 ⎯
25:16 DRWINOF
15:2 ⎯
1:0 CS [1:0]
DRWINLO [35:20]
DRWINUP [35:30]
DRWINUP [29:20]
RESERVED
DRWINOF [29:20]
RESERVED
Chip Select [1:0]
Define the lower address of window #n in physical address.
DRWINLO_ADRS = { DRWINUP [35:20], 20'HF_FFFF }
This register is the copy of DRWINLO [35:30]
Define the upper address of window #n in physical address.
DRWINUP _ADRS = { DRWINUP [35:20], 20'H0_0000 }
⎯
Define the offset address of the target DDR memory space.
DRWINOF _ADRS = { DRWINOF [29:20], 20'H0_0000 }
⎯
Define corresponding DDR channel number with CS
Initial
Value
R/W
0
R/W
0
R/O
0
R/W
⎯
⎯
0
R/W
⎯
⎯
0
R/W
CS[1:0] = 0 Channel 0 (CS0)
CS[1:0] = 1 Channel 0 (CS0)
CS[1:0] = 2 Channel 1 (CS1)
CS[1:0] = 3 Channel 1 (CS1)
NOTE: CS setting should be consistent with DDR_CTRL15 setting.
When the system receives an effective physical address, (EPA), it checks following condition for enabled window(s).
IF ( ( EPA <= DRWINUP_ADRS ) && ( EPA >= DRWINLO_ADRS) )
Then, if it is true, Corresponding DDR channel will be accessed with following DDR_EFFECTIVE_ADDRESS.
DDR_EFFECTIVE_ADDRESS = EPA – DRWINLO_ADRS + DRWINOF_ADRS
Rev. 3.1 November 1, 2005
6-5