TX4939XBG-400 Datasheet, PDF (122/740 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Address
Toshiba RISC Processor
TX4939
6.6.2. Registers for ATA1
All registers below are mapped into ATA100 CORE registers one by one, except the DMA Command register is mapped to
ATA100 CORE register, Start register and Direction Control register. Use byte, half-word, or word load/store to access
register with 8, 16, or 32 bits word, respectively
Table 6-10 Internal Registers for ATA1
Offset Address
Register Size
(bit)
Register Symbol
Register Name
ATA1
LE
BE
0x4000
0x4006
16
ATA1_DATA
DATA register ATA1 device
0x4001
0x4006
8
ATA1_Error_Ft
Error/Feature ATA1 device
0x4002
0x4005
8
ATA1_Sec
Sector Count ATA1 device
6
0x4003
0x4004
8
ATA1_LBA0
LBA Low ATA1 device
0x4004
0x4003
8
ATA1_LBA1
LBA Mid ATA1 device
0x4005
0x4002
8
ATA1_LBA2
LBA High ATA1 device
0x4006
0x4001
8
ATA1_Device
Device register ATA1 device
0x4007
0x4000
8
ATA1_St_Cmd
Status/Command ATA1 device
0x4402
0x4405
8
ATA1_Alt_DevCtl Alternate Status/Device Control ATA1 device
0x4800
0x4807
8
ATA1_DMA_Cmd DMA command for ATA1
0x4802
0x4805
8
ATA1_DMA_stat DMA Status for ATA1
0x4804
0x4800
32
ATA1_PRD_Ptr
PRD Table Pointer for ATA1
0x4c00
0x4c06
16
ATA1_Sys_Ctl_1 System Control 1 for ATA1
0x4c02
0x4c04
16
ATA1_Sys_Ctl_2 System Control 2 for ATA1
0x4c08
0x4c0e
16
ATA1_Xfer_Cnt_1 Transfer Word Count 1 for ATA1
0x4c0a
0x4c0c
16
ATA1_Xfer_Cnt_2 Transfer Word Count 2 for ATA1
0x4c10
0x4c16
16
ATA1_Sec_Cnt
Sector Count for ATA1
0x4c18
0x4c1e
16
ATA1_Strt_AddL Transfer Start Low Address for ATA1
0x4c20
0x4c26
16
ATA1_Strt_AddU Transfer Start Upper Address for ATA1
0x4c28
0x4c2e
16
ATA1_Add_Ctl
Additional Control for ATA1
0x4c30
0x4c36
16
ATA1_Lo_BCnt
Lower Burst Count for ATA1
0x4c38
0x4c3e
16
ATA1_Up_BCnt
Upper Burst Count for ATA1
0x4c88
0x4c8e
16
ATA1_PIO_Acc
PIO Access Address for ATA1
0x4c90
0x4c96
16
ATA1_H_Rst_Tim Host Reset Timer for ATA1
0x4c98
0x4c9e
16
ATA1_int_ctl
Interrupt Control for ATA1
0x4cb8
0x4cbe
16
ATA1_Pkt_Cmd
ATAPI Packet Command for ATA1
0x4cc0
0x4cc6
16
ATA1_Bxfer_cntH Bus Transfer Count High for ATA1
0x4cc8
0x4cce
16
ATA1_Bxfer_cntL Bus Transfer Count Low for ATA1
0x4cd0
0x4cd6
16
ATA1_Dev_TErr
Device Timing Error for ATA1
0x4cd8
0x4cde
16
ATA1_Pkt_xfer_ct Packet Transfer Control for ATA1
0x4ce0
0x4ce6
16
ATA1_Strt_AddT Transfer Start Top Address for ATA1
6.6.3. Registers for NAND Controller (NDFMC)
Use Double Word (LD/SD) or Word (LW/SW) load/store to access register.
Table 6-11 Internal Registers for NAND Controller (NDFMC)
Offset Address
NAND Controller (NDFMC)
LD/SD
LW/SW
LE/BE
LE/BE
0x5000
0x5000
0x5008
0x5008
0x5010
0x5010
0x5018
0x5018
0x5020
0x5020
0x5028
0x5028
Register Size (bit)
Register
Symbol
Register Name
32
NDFDTR
NAND Flash Memory Data Transfer Register
32
NDFMCR
NAND Flash Memory Mode Control Register
32
NDFSR
NAND Flash Memory Status Register
32
NDFISR
NAND Flash Memory Interrupt Status Register
32
NDFIMR
NAND Flash Memory Interrupt Mask Register
32
NDFSPR
NAND Flash Memory Strobe Pulse Width Register
Rev. 3.1 November 1, 2005
6-12