TC55VBM316AFTN Datasheet, PDF(8/15 Page) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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TC55VBM316AFTN Datasheet, PDF (8/15 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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READ CYCLE (See Note 1)

Address

A0~A18 (Word Mode)

A-1~A18 (Byte Mode)

CE1

CE2

UB , LB

DOUT

I/O1~16 (Word Mode)

I/O1~8 (Byte Mode)

Hi-Z

TC55VBM316AFTN/ASTN40,55

tRC

tACC

tOH

tCO1

tCO2

tOE

tOD

tBA

tODO

tBE

tOEE

tCOE

tBD

VALID DATA OUT

Hi-Z

WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)

Address

A0~A18 (Word Mode)

A-1~A18 (Byte Mode)

R/W

CE1

CE2

UB , LB

DOUT

I/O1~16 (Word Mode)

I/O1~8 (Byte Mode)

DIN

I/O1~16 (Word Mode)

I/O1~8 (Byte Mode)

tAS

(See Note 2)

(See Note 5)

tWC

tWP

tWR

tCW

tBW

tODW

tOEW

Hi-Z

tDS

tDH

VALID DATA IN

(See Note 3)

(See Note 5)

2002-08-05 8/15

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