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TC55VBM316AFTN Datasheet, PDF (2/15 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
BLOCK DIAGRAM
TC55VBM316AFTN/ASTN40,55
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
CE
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A17
A18
MEMORY CELL ARRAY
4,096 × 128 × 16
(8,388,608)
VDD
GND
SENSE AMP
CLOCK
GENERATOR
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A-1 A1 A3 A5
A0 A2 A4 A16
CE1
CE2
LB
CE
UB
R/W
OE
BYTE
2002-08-05 2/15