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TC55VBM316AFTN Datasheet, PDF (4/15 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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TC55VBM316AFTN/ASTN40,55
DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V)
SYMBOL PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
IIL
IOH
IOL
ILO
lDDO1
lDDO2
Input Leakage
Current
VIN = 0 V~VDD
Output High Current VOH = VDD − 0.5 V
Output Low Current VOL = 0.4 V
Output Leakage
Current
CE1 = VIH or CE2 = VIL or LB = UB = VIH or
R/W = VIL or OE = VIH, VOUT = 0 V~VDD
Operating Current
CE1 = VIL and CE2 = VIH and
R/W = VIH, LB = UB = VIL,
IOUT = 0 mA,
Other Input = VIH/VIL
CE1 = 0.2 V and CE2 = VDD − 0.2 V and
R/W = VDD − 0.2 V, LB = UB = 0.2 V,
IOUT = 0 mA,
Other Input = VDD − 0.2 V/0.2 V
tcycle
MIN
1 µs
tcycle
MIN
1 µs
  ±1.0 µA
−0.5 
2.1 
 mA
 mA
  ±1.0 µA
  35
mA
 8
  30
mA
 3
IDDS1
1) CE1 = VIH or CE2 = VIL (at BYTE ≥ VDD − 0.2 V or ≤ 0.2 V)
2) LB = UB = VIH (at BYTE ≥ VDD − 0.2 V)


1 mA
IDDS2
Standby Current
1)
CE1 = VDD − 0.2 V, CE2 =
VDD − 0.2 V (at BYTE ≥ VDD
VDD =
3.3 V ± 0.3 V
Ta = −40~85°C


10
− 0.2 V or ≤ 0.2 V)
Ta = 25°C
 0.7 
2) CE2 = 0.2 V (at BYTE ≥ VDD
µA
− 0.2 V or ≤ 0.2 V)
VDD = 3.0 V Ta = −40~40°C  
2
3) LB = UB = VDD − 0.2 V,
CE1 = 0.2 V, CE2 = VDD − 0.2
V (at BYTE ≥ VDD − 0.2 V)
Ta = −40~85°C   5
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
CIN
COUT
Input Capacitance
Output Capacitance
VIN = GND
VOUT = GND
Note: This parameter is periodically sampled and is not 100% tested.
MAX
10
10
UNIT
pF
pF
2002-08-05 4/15
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