TC55VBM316AFTN Datasheet, PDF (1/15 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55VBM316AFTN/ASTN40,55
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288
words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this
device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and
low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in
low-power mode at 0.7 µA standby current (at VDD = 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted
high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB )
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of −40° to 85°C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package
(TSOP).
FEATURES
• Low-power dissipation
Operating: 9 mW/MHz (typical)
• Single power supply voltage of 2.3 to 3.6 V
• Power down features using CE1 and CE2
• Data retention supply voltage of 1.5 to 3.6 V
• Direct TTL compatibility for all inputs and outputs
• Wide operating temperature range of −40° to 85°C
• Standby Current (maximum):
3.6 V
3.0 V
10 µA
5 µA
PIN ASSIGNMENT (TOP VIEW)
48 PIN TSOP
1
48
24
25
(Normal)
• Access Times (maximum):
TC55VBM316AFTN/ASTN
40
55
Access Time
40 ns
55 ns
CE1 Access Time
40 ns
55 ns
CE2 Access Time
40 ns
55 ns
OE Access Time
25 ns
30 ns
• Package:
TSOPᶗ48-P-1220-0.50 (AFTN) (Weight:0.51 g typ)
TSOPᶗ48-P-1214-0.50 (ASTN) (Weight:0.36 g typ)
PIN NAMES
A0~A18
A-1~A18
CE1 , CE2
R/W
OE
LB , UB
I/O1~I/O16
BYTE
V_DD
GND
NC
OP*
Address Inputs (Word Mode)
Address Inputs (Byte Mode)
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Byte (×8 mode) Enable
Power
Ground
No Connection
Option
*: OP pin must be open or connected to GND.
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
A15 A14 A13 A12 A11 A10 A9 A8 NC NC R/W CE2 OP UB LB A18
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A17 A7 A6 A5 A4 A3 A2 A1 A0 CE1 GND OE I/O1 I/O9 I/O2 I/O10
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
I/O3 I/O11
I/O4 I/O12 V_DD
I/O5
I/O13 I/O6 I/O14 I/O7
I/O15 I/O8
I/O16 _GND
/A-1
BYTE
A16
2002-08-05 1/15