TC35274 Datasheet, PDF (8/13 Pages) Toshiba Semiconductor – TOSHIBA MPEG-4 Video Decoder LSI

Preliminary
MPEG-4 Video Decoder LSI
TC35274
/HCS
HADDR
/HWR
/HWAIT
HDAT
(a)
T_CSS
T_ADS
T_WTAD
T_WTID
T_DTWS
(b)
(c)
T_CSH
T_ADH
T_RDH
T_RR
T_DTID
Fig. 4 Write Operation in handshake mode
3.1.2 Synchronized access mode
In this mode, a host CPU accomplishs an access to TC35274 in the specified period without a
handshake. However, if the host CPU accesses to the embedded DRAM in TC35274, it has to check
whether the next access is available or not by checking a status register at every 8 accesses.
Fig.5 shows the timing diagram of a read operation. A read access starts by asserting both a chip
select signal (/HCS) and a read signal (/RD) (timing (a)). After the specified cycles indicated as Tacs,
the host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD
(timing (b)).
Fig.6 shows the timing diagram of a write operation. A write access starts by asserting both /HCS
and a write signal (/WR) (timing (a)). After the specified cycles, the host CPU finishes the write
operation by negating both /HCS and /HWR (timing (b)).
TOSHIBA Confidential
8/13
Version 0.90
2000-4-27