TC35274 Datasheet, PDF (10/13 Pages) Toshiba Semiconductor – TOSHIBA MPEG-4 Video Decoder LSI

Preliminary
MPEG-4 Video Decoder LSI
TC35274
3.1.3 Interrupt
An interrupt to the external host CPU is performed as follows.
(a) HINT Active
When an interrupt is requested by TC35274, HINT becomes high (timing (a)).
(b) Clear HINT
The host CPU detects the interrupt request by HINT. The CPU also detects the interrupt
causes by reading an interrupt status register in the host interface of TC35274. When the CPU
reads the register at the timing (b), The CPU detects the interrupt causes occurring during the
timing (a) and (b). HINT is cleared when the CPU reads the interrupt status register.
(c) Multiple Interrupt
Even if another interrupt is requested during the timing (b) and (c), The assertion of HINT is
suspended to the timing (c).
HINT
/HCS
HADDR
/HRD
/H W A IT
H D AT
(a)
(b)
(c)
T_RRD
T_ACS
Fig. 7 Interrupt Operation
TOSHIBA Confidential
10/13
Version 0.90
2000-4-27