TC35274 Datasheet, PDF (13/13 Pages) Toshiba Semiconductor – TOSHIBA MPEG-4 Video Decoder LSI

Preliminary
MPEG-4 Video Decoder LSI
TC35274
Table 8 Display Interface Timing
Parameter
Description
Min
T_CYCLE
Cycle time of DISPCLK
100
T_SETUP
Setup time of DISPHSYN and DISPVSYN
2
T_HOLD
Hold time DISPHSYN and DISPVSYN
2
T_DELAY
Delay time of DISPBLK and DISPPXL
* When system clock is 40MHz, DSPCLK has to be less than 10MHz.
Max
(T_SYSCLK*3)+15
Unit
ns
ns
ns
ns
4. Electric Specifications
4.1 TBD.
TOSHIBA Confidential
13/13
Version 0.90
2000-4-27