TC35274 Datasheet, PDF (5/13 Pages) Toshiba Semiconductor – TOSHIBA MPEG-4 Video Decoder LSI

Preliminary
MPEG-4 Video Decoder LSI
TC35274
Signal Name
/RESET
STANDBY
In/Out
In
In
Table 1. System Control Signals
Bit Width
1
1
Description
System Reset Input (Low Active). When the LSI is reset, this terminal has
to be low for more than 16 clock cycles. When power on, the LSI has to be
reset after PLL locked. It takes approximately 100us until the PLL locked.
System Standby Input (High Active).
Stop clock distribution to the LSI. After standby, system reset is required.
“0” : Active.
“1” : Standby.
Table 2. PLL Control Signals
Signal Name
PLLFN
PLLDIV[2:0]
PLLAVD
PLLAVS
In/Out
In
In
In
In
Bit Width
1
3
1
1
Description
Reference Clock Input.
It has to be 13.00MHz to 20MHz with +/- 10% duty.
System clock frequency select. System Clock = PLLFN * N.
“00” : N=1.0.
“01” : N=1.5.
“10” : N=2.0
“11” : N=2.5.
Analog PLL Power(VDD).
Analog PLL Ground(VSS).
Signal Name
/HCS
/HWR
/HRD
HADDR[6:0]
HDAT[15:0]
HWAIT
HINT
In/Out
In
In
In
In
In/Out
Out
Out
Bit Width
1
1
1
7
16
1
1
Table 3. Host Interface
Description
Chip enable input ( low active).
“0” : Chip select.
“1” : Non operation.
Write strobe (low active).
“0” : Write operation.
“1” : Non operation.
Read Strobe (low active).
“0” : Read operation.
“1” : Non operation.
Address signal.
Data signal.
Bus wait signal (low active).
“0” : Wait.
“1” : Non wait.
Interrupt signal (high active).
“0” : Non operation.
“1” : Interrupt Operation.
Table 4 Video Display Interface
Signal Name
DISPCLK
/DISPHSYNC
/DISPVSYNC
/DISPBLK
DISPPIXEL
In/Out
In
In
In
Out
Out
Bit Width
1
1
1
1
8
Description
Clock signal from display.
HSYNC signal from display.
VSYNC signal form display.
Blanking signal to display.
Luminance (Y) and chrominance (Cb,Cr) signal output.
TOSHIBA Confidential
5/13
Version 0.90
2000-4-27