TC35274 Datasheet, PDF (7/13 Pages) Toshiba Semiconductor – TOSHIBA MPEG-4 Video Decoder LSI

Preliminary
MPEG-4 Video Decoder LSI
TC35274
3. Interface Specifications
3.1 Host Interface
An external host CPU can access to TC35274 via a host interface. The access timing of a read,
a write, and an interrupt operation are explained below. The host interface has two access modes;
handshake access mode and synchronized access mode.
3.1.1 Handshake access mode
In this mode, the host CPU has to finish an access operation after a waiting signal (/HWAIT)
becomes high.
Fig.3 shows the timing diagram of a read operation. A read access starts by asserting both a chip
select signal (/HCS) and a read signal (/RD) (timing (a)). At this timing, /HWAIT becomes low. When
the read data are ready, /HWAIT becomes high (timing (b)). The host CPU gets the read data and
finishes the read operation by negating both /HCS and /HRD (timing (c)).
Fig.4 shows the timing diagram of a write operation. A write access starts by asserting both /HCS
and a write signal (/WR) (timing (a)). At this timing, /HWAIT becomes low. When TC35274 gets the
write data, /HWAIT becomes high (timing (b)). After that, the host CPU finishes the write operation by
negating both /HCS and /HWR (timing (c)).
/HCS
HADDR
/HRD
/HWAIT
HDAT
(a)
T_CSS
T_ADS
(b)
(c)
T_CSH
T_ADH
T_RR
T_WTAD
T_WTID
T_DTVD
T_RDH
T_DTRS
T_DTID
T_DTOD
Fig. 3 Read Operation in handshake mode
TOSHIBA Confidential
7/13
Version 0.90
2000-4-27