TMP92CZ26AXBG Datasheet, PDF (534/767 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CZ26A
LCDCTL0 <LCP0OC> is used to control the output timing of the LCP0 signal. When
<LCP0OC>=0, the LCP0 signal is always output. When <LCP0OC>=1, the LCP0
signal is output only when valid data is output.
LCP0 signal LCP0OC=1
LCP0 signal LCP0OC=0
LCD Control 0 Register
7
6
5
4
3
2
1
0
LCDCTL0
(0285H)
bit Symbol
Read/Write
Reset State
Function
PIPE
ALL0
R/W
0
0
PIP function Segment
0:Disable data
1:Enable 0: Normal
1: Always
output “0”
FRMON
0
Frame
divide
setting
0: Disable
1: Enable
−
R/W
0
Always
write “0”
DLS
0
FR signal
LCP0/Line
selection
0:Line
1:LCP0
LCP0OC START
R/W
0
0
LCP0(Note LCDC
0: Always operation
output
0: Stop
1: At valid 1: Start
data only
LLOAD
width
0: At setting
in register
1: At valid
data only
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
The phase of the LCP0 signal can be inverted by the setting of LCDCTL1<LCP0P>.
LVSYNC
LHSYNC
LLOAD
LGOEn
LFR
All signal changes
LCP0P=0
LCP0
LCP0P=1
LCP0
LD23-LD0
LCD Control 1 Register
7
6
5
4
3
LCDCTL1
(0286H)
bit Symbol
Read/Write
Reset State
Function
LCP0P
1
LCP0
phase
0: Rising
1: Falling
LHSP
LVSP
R/W
0
1
LHSYNC
phase
0: Rising
1: Falling
LVSYNC
phase
0: Rising
1: Falling
LLDP
0
LLOAD
phase
0: Rising
1: Falling
92CZ26A-533
2
1
0
LVSW1 LVSW0
R/W
0
0
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
2007-11-13