TMP92CZ26AXBG Datasheet, PDF (193/767 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CZ26A
(5) Recovery cycle (data hold time) control
For some memory, the data hold time after when the CE or OE signal is asserted in a
read cycle is defined by the AC specification. This may lead to data conflicts. Thus, to
avoid this problem, a single dummy cycle can be inserted immediately after an access
cycle for the CSm space by setting the BmCSH<BmREC> bit to 1.
This single dummy cycle is inserted when another CS space is accessed in the next bus
cycle.
BnCSH<BnREC>
0
No dummy cycle is inserted (Default).
1
Dummy cycle is inserted.
• When no dummy cycle is inserted (0 wait state)
SDCLK
A23 to A0
CSm
CSn
RD
• When a single dummy cycle is inserted (0 wait state)
Dummy
SDCLK
A23 to A0
CSm
CSn
RD
92CZ26A-192
2007-11-13