TMP92CZ26AXBG Datasheet, PDF (189/767 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CZ26A
Table 3.8.3 Valid Block Sizes for Each CS Space
Size
(Byte) _{256 512 32 K 64 K 128 K 256 K 512 K 1 M 2 M 4 M 8 M}
CS space
CS0
○○○○
Δ
Δ
Δ
Δ
Δ
CS1
○○
○
Δ
Δ
Δ
Δ
Δ
Δ
CS2
○○
Δ
Δ
Δ
Δ
Δ
Δ
Δ
CS3
○○
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Note: The “Δ” symbol indicates the sizes that may not be programmable depending on the combination of the values
of the Memory Start Address and Memory Address Mask registers.
(e) Priorities of the address spaces
When the specified address space overlaps with the on-chip memory area, the
priority order of the address spaces are as follows:
On-chip I/O > On-chip memory > CS0 space > CS1 space > CS2 space > CS3 space
(f) Specifying the number of wait states and the bus width for the address locations
outside the CS0 to CS3 spaces
The BEXCSL and BEXCSH registers specify the data bus width and number of wait
states when an adress outside the CS0 to CS3 spaces ( CSEX space) is accessed. These
registers are always enabled for the CSEX space.
92CZ26A-188
2007-11-13