TMP92CZ26AXBG Datasheet, PDF (453/767 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CZ26A
3.16.8 USB Device answer
The USB controller (UDC) sets various register and initialization in the UDC in
detecting of hardware reset, detecting of USB bus reset, and enumeration answer.
Each condition is explained below.
(1) bus reset detect condition.
When the UDC detects a bus reset on the USB signal line, it initializes internal
register, and it prepares enumeration operation from USB host. After detecting a
USB reset, the UDC sets ENDPOINT0 to control transfer type 8-byte payload and
default address for using default pipe. Any endpoint other than this is prohibited.
Register name
ENDPOINT STATUS
EP0
Except for EP0
Initial value
40H
5CH
(2) Detail of STATUS register
Status register that has been prepared for each endpoint shows the condition of
each endpoint in the UDC.
Each condition affects the various USB transfers. Refer to chapter 5 for the
changing conditions for each transfer type.
EPx_STATUS register value is 0 to 3, and its shows conditions are shown. 0 to 4 are
the results of various transfers. It can be confirmed previous result that is transferred
to endpoint by confirming from external of UDC.
0 READY
1 DATAIN
2 FULL
3 TX_ERR
4 RX_ERR
These conditions mean that the endpoint is operating normally. The meaning that
is showed is different for each transfer mode. Therefore, please refer to each transfer
mode column below.
92CZ26A-452
2007-11-13