HN4B101J Datasheet, PDF (5/6 Pages) Toshiba Semiconductor – Transistor Silicon PNP / NPN Epitaxial Type (PCT Process)

Common
1000
r_th – t_w
HN4B101J
100
10
Curves apply only to limited areas of thermal resistance.
Single nonrepetitive pulse Ta = 25°C
Mounted on an FR4 board (glass-epoxy; 1.6 mm thick; Cu area, 645 mm²)
1
0.001
0.01
0.1
1
10
Pulse width t_w (s)
100
1000
Permissible Power Dissipation for
Simultaneous Operation
0.7
DC operation
Ta = 25°C
0.6
Mounted on an FR4 board (glass-epoxy; 1.6
mm thick; Cu area, 645 mm²)
0.5
0.4
0.3
0.2
0.1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
Permissible power dissipation for Q1
P_C (W)
Collector power dissipation at single-device operation is
0.55 W.
Collector power dissipation at single-device value at
dual operation is 0.31 W.
Collector power dissipation at dual operation is set to
0.62 W.
5
2006-11-13