TMP92CM27 Datasheet, PDF (366/502 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CM27
(3-2) Interrupt status register
Register read 4 interrupt status and clear interrupt.
This register is cleared to “0” by writing “1” to applicable bit. Status of this register show
interrupt source state. This register can confirm changing of interrupt condition, even if
interrupt enable register is masked.
HSC0IS Register
7
6
5
4
3
2
1
0
HSC0IS
(0C08H)
bit Symbol
Read/Write
After Reset
TENDIS0
0
RENDIS0 RFWIS0
R/W
0
0
RFRIS0
0
Read
Read
Read
Read
0:no interrupt 0:no interrupt 0:no interrupt 0:nointerrupt
Function
1:interrupt
Write
1:interrupt
Write
1:interrupt
Write
1:interrupt
Write
0:Don’t care 0:Don’t care 0:Don’t care 0:Don’t care
1:clear
1:clear
1:clear
1:clear
15
14
13
12
11
10
9
8
bit Symbol
(0C09H) _Read/Write
After Reset
Function
7
HSC1IS
(0C28H)
bit Symbol
Read/Write
After Reset
Function
15
bit Symbol
(0C29H) _Read/Write
After Reset
Figure 3.12.5 HSC0IS Register
HSC0IS Register
6
5
4
3
2
1
0
TENDIS1
0
RENDIS1 RFWIS1
R/W
0
0
RFRIS1
0
Read
Read
Read
Read
0:no interrupt 0:no interrupt 0:no interrupt 0:nointerrupt
1:interrupt 1:interrupt 1:interrupt 1:interrupt
Write
Write
Write
Write
0:Don’t care 0:Don’t care 0:Don’t care 0:Don’t care
1:clear
1:clear
1:clear
1:clear
14
13
12
11
10
9
8
Function
Figure 3.12.6 HSC1IS Register
92CM27-310
2005-04-20