TMP92CM27 Datasheet, PDF (13/502 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CM27
3.1.2 Reset Operation
When resetting the TMP92CM27, ensure that the power supply voltage is within the operating
voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the
RESET input low for at least 20 system clocks (16 µs at fc = 40 MHz).
At reset, since the clock doubler (PLL) is bypassed and clock-gear is set to 1/16, system clock
operates at 1.25 MHz (fc = 40 MHz).
When the reset has been accepted, the CPU performs the following:
• Sets the program counter (PC) as follows in accordance with the reset vector stored at
address FFFF00H to FFFF02H:
PC<7:0>
← data in location FFFF00H
PC<15:8> ← data in location FFFF01H
PC<23:16> ← data in location FFFF02H
• Sets the stack pointer (XSP) to 00000000H.
• Sets bits <IFF2:0> of the status register (SR) to “111"
(thereby setting the interrupt level mask register to level 7).
• Clears bits <RFP1:0> of the status register to “00”
(there by selecting register bank 0).
When the reset is released, the CPU starts executing instructions according to the program
counter settings. CPU internal registers not mentioned above do not change when the reset is
released.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
• Initializes the internal I/O registers as table of “special function register” in section 5.
• Sets the port pins, including the pins that also act as internal I/O, to general-purpose
input or output port mode.
Internal reset is released as soon as external reset is released.
The operation of memory controller cannot be insured until power supply becomes stable
after power-on reset. The external RAM data provided before turning on the TMP92CM27 may
be spoiled because the control signals are unstable until power supply becomes stable after
power-on reset.
VCC (3.3 V)
RESET
High-frequency oscillation stabilized time
+20 system clock
0 s (Min)
Figure 3.1.1 Power on Reset Timing Example
92CM27-11
2005-04-20