TMP92CM27 Datasheet, PDF (171/502 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CM27
Port L register
7
6
5
4
3
2
1
0
PL bit Symbol PL7
PL6
PL5
PL4
PL3
PL2
(0054H) _Read/Write
R/W
PL1
PL0
After reset
Data from external port(Output latch register is set to “1”)
PLCR bit Symbol
(0056H) _Read/Write
After reset
7
PL7C
0
6
PL6C
0
Port L Control register
5
PL5C
0
4
3
2
PL4C PL3C
PL2C
W
0
0
0
Refer to following table
1
PL1C
0
0
PL0C
0
PLFC
(0057H)
bit Symbol
Read/Write
After reset
Function
7
PL7F
0
6
PL6F
0
Port L Function register
5
PL5F
0
4
3
2
PL4F PL3F
PL2F
W
0
0
0
Refer to following table
1
PL1F
0
0
PL0F
0
7
PLFC2
(0055H)
bit Symbol
Read/Write
After reset
Function
6
PL6F2
0
Port L Function register 2
5
PL5F2
0
4
3
2
PL4F2 PL3F2 PL2F2
W
0
0
0
Refer to following table
1
PL1F2
0
0
PL0F2
0
Port L function setting
<PLxF2> <PLxF> <PLxC>
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
PL7
Input port
Output port
Reserved
PG13
PL6
Input port
Output port
Reserved
PG12
Reserved
PL5
Input port
Output port
Reserved
PG11
Reserved
PL4
Input port
Output port
Reserved
PG10
HSSI1
PL3
PL2
Input port Input port
Output port Output port
Reserved Reserved
PG03
PG02
Reserved SCLK3/ CTS3
PL1
Input port
Output port
Reserved
PG01
Reserved
PL0
Input port
Output port
Reserved
PG00
RXD3
1
0
1
1
1
0
HSCLK1
Reserved
HSSO1
Reserved
Reserved
Reserved
Reserved
Reserved
SCLK3
Reserved
TXD3
(O.D Dis)
Reserved
Reserved
Reserved
1
1
1
Reserved Reserved Reserved TA7OUT
Reserved
TXD3
(O.D Ena)
Reserved
Note 1) Read-modify-write is prohibited for PLCR, PLFC and PLFC2.
Note 2) RXD3, SCLK3 and CTS3 input are inputted into the serial bus interface 3 irrespective of a functional
setup of a port.
Note 3) HSSI1 input are inputted into the high speed serial channel 0 irrespective of a functional setup of a port.
Note 4) PL1 does not have a register for 3-state/open drain setup.
Moreover, there is no open drain function at the time of an output port.
Figure 3.5.46 Port L register
92CM27-115
2005-04-20