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SSM3K324R Datasheet, PDF (2/6 Pages) Toshiba Semiconductor – TOSHIBA Field-Effect Transistor Silicon N-Channel MOS Type
Electrical Characteristics (Ta = 25°C)
SSM3K324R
Characteristic
Symbol
Test Conditions
Min Typ. Max Unit
Drain-source breakdown voltage
Drain cut-off current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Drain–source ON-resistance
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Switching time
Turn-on time
Turn-off time
Drain-source forward voltage
V (BR) DSS ID = 1 mA, VGS = 0 V
30


V
V (BR) DSX ID = 1 mA, VGS = −12 V
(Note 5) 18


IDSS
VDS = 24 V, VGS = 0 V


1
µA
IGSS
VGS = ± 10 V, VDS = 0 V


±10
µA
Vth
VDS = 3 V, ID = 1 mA
0.4

1.0
V
Yfs
VDS = 3 V, ID = 2.0 A
(Note 4)  10.5 
S
ID = 2.0 A, VGS = 4.5 V
(Note 4) 
45
56
RDS (ON) ID = 1.0 A, VGS = 2.5 V
(Note 4) 
55
72
mΩ
ID = 0.5 A, VGS = 1.8 V
(Note 4) 
69 109
Ciss

200

Coss
VDS = 10 V, VGS = 0 V, f = 1 MHz

40

pF
Crss

13

Qg
Qgs1
Qgd
VDS = 10 V, ID = 2.4 A
VGS = 4.5 V

2.2


0.5

nC

0.9

ton
VDD = 10 V, ID = 2.0 A,
toff
VGS = 0 to 2.5V, RG = 4.7 Ω

9

ns

9.5

VDSF
ID = -4.0 A, VGS = 0 V
(Note 4) 
-0.8 -1.2
V
Note 4: Pulse test.
Note 5: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the
drain-source breakdown voltage is lowered in this mode.
(a) Test Circuit
2.5 V
IN
0
10 µs
(b) VIN
OUT
VDD = 10 V
RG = 4.7 Ω
Duty ≤ 1%
VIN: tr, tf < 5 ns
Common Source
Ta = 25°C
(c) VOUT
VDD
2.5V
0V
VDD
VDS (ON)
10%
90%
90%
10%
tr
tf
ton
toff
Usage Considerations
Let Vth be the voltage applied between gate and source that causes the drain current (ID) to below (1 mA for the
SSM3K324R). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower than
Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on).
Take this into consideration when using the device.
2
2012-12-21