TM4C1233E6PM Datasheet, PDF (999/1214 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233E6PM Microcontroller
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CLKRIS RIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
0
Name
reserved
CLKRIS
RIS
Type
RO
RO
RO
Reset
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Timeout Raw Interrupt Status
Value Description
0 No interrupt.
1 The clock timeout interrupt is pending.
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
Master Raw Interrupt Status
Value Description
0 No interrupt.
1 A master interrupt is pending.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
June 12, 2014
999
Texas Instruments-Production Data